The present invention relates to a test facilitation technique incorporated into a semiconductor integrated circuit, and to a technique effective for application to a semiconductor integrated circuit in which, for example, JTAG (Joint Test Action Group) has been adopted as a boundary scan standard.
As a test facilitation technique used for a semiconductor integrated circuit, a structure has been widely adopted which performs a test operation while a scan path is caused to transfer scan data in synchronism with a scan clock upon the test operation, and scans out the result thereof.
Japanese Patent Application Laid-Open No. Hei 3-42850 has described an invention wherein when a test mode is specified or designated from the outside of a semiconductor integrated circuit, scan data is automatically generated thereinside and thereby a burn-in test is allowed through a scan path. An invention has been described in Japanese Patent Application Laid-Open No. Hei 6-201780, wherein a test pattern generator is placed at the input of a scan chain and a test output compressor is placed at the output of the scan chain, whereby the shortening of a test time interval is set up. Japanese Patent Application Laid-Open No. Hei 5-264664 has described a technique related to boundary scan using a TAP controller and wherein a clock is supplied only to each of registers to be tested in accordance with the result of decoding of an instruction issued from the TAP controller, thereby achieving low power consumption.
Japanese Patent Application Laid-open No. Hei 5-264664 has disclosed a description related to an invention wherein a test enable signal and a test clock signal are respectively supplied in parallel to a plurality of semiconductor integrated circuits each having a self-test circuit incorporated therein and self-test mechanisms are simultaneously operated to carry out troubleshooting, whereby a test time interval is shortened. Japanese Patent Application Laid-Open No. Hei 8-220192 has disclosed a description related to an invention wherein inspection control LSI is implemented on a single circuit printed board together with a plurality of tested LSI which are addressed and have chains of scannable flip-flop respectively, and the inspection control LSI has a pseudo-random number generator and a code compressor and writes a pseudo random number into its corresponding flip-flop upon scan-in and supplies data of each flip-flop to the code compressor upon scan-out, thereby making it possible to achieve the facilitation and speeding up of troubleshooting.
The present inventors have investigated or discussed a device test on a semiconductor integrated circuit equipped with a plurality of pieces of circuit modules (corresponding to functional units also called functional modules) relatively large in logic scale as in a memory, a CPU or the like. According to the result of discussions, they have revealed the necessity for reducing the amount of test data to be supplied from the outside and the amount of data about test results to be outputted to the outside and parallelizing test operations for circuit modules to thereby shorten test times with a view toward improving the efficiency of testing. In order to reduce a logical and physical scale of a circuit necessary for testing to the utmost, a circuit for performing the input and output of test data and result data to and from the respective circuit modules needs to be shared between the respective circuit modules. Further, when JTAG is adopted as the standard for boundary scan for inspecting an electrical connection between a semiconductor integrated circuit to which a surface mounting package like BGA (Ball Grid Array) is applied, and a printed circuit board, such a JTAG controller as used for the boundary scan alone is appropriated to other tests. Thus, this will be useful to reduce the logical and physical scale of the test circuit. Any prior art will not be enough for these points.
An object of the present invention is to provide a semiconductor integrated circuit capable of reducing the amount of test data to be supplied from the outside and the amount of data about test results to be outputted to the outside in order to test a plurality of circuit modules, and shortening the time required to test the plurality of circuit modules.
Another object of the present invention is to provide a semiconductor integrated circuit wherein the scale of a test circuit required to test a plurality of circuit modules can be reduced as small as possible.
A further object of the present invention is to provide design data capable of facilitating the design of a semiconductor integrated circuit which implements the shortening of a test time and a reduction in the scale of a test circuit.
The above, and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application will be described in brief as follows:
[1] A semiconductor integrated circuit comprises a single semiconductor chip including a plurality of circuit modules each provided with a test input terminal, a test output terminal and a test control terminal, a test path which connects the test output terminal of one circuit module to the test input terminal of the other circuit module to thereby form a test signal chain, and a test interface circuit connected to the test path. Each circuit module has a tested circuit, a test register circuit and a test control circuit. The test register circuit is connected to the test path through the test input terminal and the test output terminal and permits input and output to and from the test control circuit. The test control circuit receives a start for a test on the tested circuit from the test control terminal to thereby perform the test using test control information outputted from the test register circuit and supplies information about the result of test to the test register circuit. The test interface circuit supplies the test control information to the test register circuit from the outside through a test path and outputs the information about the result of test from the test register circuit to the outside through the test path.
When each of the tested circuits is tested, test control information can be externally inputted to a test interface circuit, and the test control information can be set to each of the test register circuits in all the circuit modules to be tested, through a test path corresponding to a test signal chain from the test interface circuit. Thereafter, when an instruction for a test operation is given to each of the test control circuits through a control terminal, a test circuit allows the tested circuits to be tested based on the test control information on a parallel basis. Information about test results are held in each individual test register circuits. Afterwards, the information held in the test register circuits in all the circuit modules to be tested are read into the test interface circuit through the test path corresponding to the test signal chain and outputted to the outside. Thus, the test operations for the circuit modules can be parallelized and hence a test time interval can be shortened. Since the test interface circuit, which performs the input and output of the test control information and test result data to and from the circuit modules, can be shared between the respective circuit modules, this can contribute even to a reduction in logical/physical scale of a circuit necessary for testing.
[2] A test pattern generator and a compressor may be adopted for the test control circuit. The test pattern generator generates a test pattern for each test circuit, based on the test control information inputted to the test register circuit. The compressor compresses the result of operation of the tested circuit to thereby generate information about the result of test and supplies the same to the test register circuit. The test control information may be placed as a test command for specifying or indicating the contents of each test operation. The test pattern generator decodes the test command and thereby generates a test pattern.
Thus, the amount of the test control information sent from the test interface circuit to each of the test register circuits and the amount of operation-result information sent from the test register circuit to the test interface circuit can be reduced, thereby making it possible to contribute to an improvement in test efficiency.
[3] If the control terminals of the plurality of circuit modules are connected in common and coupled to the test interface circuit, then instructions for test operations can be given to the plurality of circuit modules on a parallel basis and besides the number of signals for their instructions can be limited to the minimum.
[4] The test path may adopt, for example, a configuration of a scan path which series-connects the plurality of test register circuits with the test interface circuit as a base point and is fed back to the test interface circuit. At this time, a transfer control clock may be generated by the test interface circuit.
In this case, the test register circuit may comprise, for example, a plural-bits type shift register having a serial input terminal connected to the test input terminal, a serial output terminal connected to the test output terminal, a parallel output terminal connected to the pattern generator, and a parallel input terminal connected to the compressor.
The test path is not limited to the case where paths having connected the test register circuits in series are formed in a single system. They may comprise plural systems. If configured in the plural systems, then the time required to transfer the test control information and the test result information through the test path can be further shortened.
[5] If one of the plurality of circuit modules is, for example, a cache memory or a random access memory, then the efficiency of a memory test which requires time for testing in general, can be improved, and the effect of improving test efficiency can be taken out to the maximum.
When the plurality of circuit modules include a first circuit module connected to a common bus, and a second circuit module connected to the first circuit module and disconnected from the common bus, an efficient test can be made even on the second circuit module on which a test cannot be made via the common bus, in a manner similar to the first circuit module.
Such a second circuit module is often used as a local memory such as a local data buffer in a controller for processing communication-system and storage-system data. Assuming such a case, a memory test can be efficiently made even on a local memory on which a test cannot be made via a common bus, in such a system LSI as brought into system on-chip.
[6] The test interface circuit has, for example, a clock terminal, a mode terminal, a data input terminal and a data output terminal as external terminals. The test interface circuit may be configured in such a manner that when a first operation mode is specified through the mode terminal, it captures information supplied to the data input terminal and delivers the captured information to the test path, when a second operation mode is specified through the mode terminal, it captures information supplied to the data input terminal and decodes the captured information to thereby output a control signal to the test control terminal, and when a third operation mode is specified through the mode terminal, it captures information of each test register circuit through the test path and outputs the same from the data output terminal to the outside.
Described more specifically, the test interface circuit having the above-described specific configuration may perform the input/output of a signal in accordance with a procedure which complies with the standard of IEEE1149.1. This standard is based on JTAG which is the standard for the boundary scan. Since such a JTAG controller as used for the boundary scan can be shared for a principal interface function of a test interface circuit, it is useful for the effective use of JTAG controller or a further reduction in the scale of a testing circuit.
[7] Judging the design of the semiconductor integrated circuit from the viewpoint of its facilitation, design data for the circuit modules or design data for the semiconductor integrated circuit itself may be provided as so-called IP (Intellectual Property) modules. The IP modules are roughly classified into a hard IP module having even circuit""s mask pattern data or graphics-drawing data together with function descriptive data such as HDL (Hardware Description Language), RTL (Register Transfer Language), and a soft IP module comprised principally of function descriptive data. Circuit module data like the IP modules is circuit module data for designing an integrated circuit to be formed on a semiconductor chip, by using a computer, and is stored in and provided from a storage medium so as to be readable by the computer.
Circuit module data includes graphics pattern data or function descriptive data for forming, on the semiconductor chip, a test input terminal, a test output terminal, a test control terminal, a normal interface terminal, at least one tested circuit connected to the normal interface terminal, at least one test register circuit which inputs information from the test input terminal and outputs the information to the test output terminal, and at least one test control circuit which receives a start for a test on the tested circuit from the control terminal to thereby perform the test using test control information outputted from the test register circuit and supplies information about the result of test to the test register circuit.
The scale of each IP module might reach up to an LSI level. When the scale is regarded in this way, the items of circuit module data are respectively provided for a plurality of circuit modules different in tested circuit from one another. Further, test path data used as graphics pattern data or function descriptive data for forming, on a semiconductor chip with the plurality of circuit modules formed thereon, a test path for connecting a test output terminal of one circuit module to a test input terminal of another circuit module to thereby constitute a test signal chain is provided for each circuit module. Furthermore, test interface circuit information may further be included as graphics pattern data or function descriptive data for forming, on the semiconductor chip, a test interface circuit which supplies the test control information from the outside to the test register circuit through the test path and outputs information about the result of test from the test register circuit to the outside through the test path.
Typical ones of various inventions of the present inventions have been shown in brief. However, the various inventions of the present application and specific configurations of these inventions will be understood from the following description.